1. Technical Field
The present invention relates to semiconductor devices, and more particularly to a device and method for enhancing performance in complementary metal oxide semiconductor (CMOS) technology.
2. Description of the Related Art
Metal-gate high dielectric constant (hi-K) and poly-silicon fully silicided (FUSI) gate electrode stack field effect transistors (FETs) are attracting substantial interest for continued complementary metal oxide semiconductor (CMOS) scaling. One major problem to date with both techniques is the ability to set a proper threshold voltage (Vt) for the NFET device without greatly lowering the active channel doping concentration.
This effect is dependant upon the position of the Fermi level in a metal hi-K or FUSI gate stack, which tends to be mid-gap versus in a conventional poly-silicon gate electrode, where the Fermi level resides at the band gap edge. Eliminating or lowering the channel doping will greatly worsen the short-channel control in the device.
Also, a technique which is not selective will in general move one FET Vt in the right direction (i.e., NFET), but will move the other FET Vt in the wrong direction (i.e., PFET). Dual-metal integration schemes have been proposed, but these are more challenging from a process integration standpoint than conventional CMOS.